Full form of LDO is, “Low-Dropout linear regulators”.
Linear regulators are a gainful means to supply a steady and regulated output voltage, with the design easiness and few external components in the circuit. If the output current is less than few amps and the output voltage is near to that of the input, LDO’s deliver the best cost-performance.
Low-Dropout linear regulators |
As compare to DC-DC switching converters, LDO regulators do not produce ripple, therefore they gives a ripple free supply voltage, and need few design steps.
Advantages of LDO
The advantages of a low dropout voltage regulator over other DC to DC regulators contain the non-availability of switching noise (as no switching takes place), reduced device size (as inductors or transformers are no required), and better design ease (usually includes a reference, an amplifier, and a pass element).Disadvantages of LDO
The disadvantage is that, unlike switching regulators, linear DC regulators dissipate power, and thus heat in order to regulate the output voltage.LDO architecture
The LDO explanation starts with the dropout voltage, which is the minimum voltage required through the regulator to keep maintain the regulation. For example, a 3.3 V LDO regulator with 1 V dropout will need a minimum input of 4.3 V. To know the meaning of voltage drop across the LDO, let’s look at the essential LDO architecture with a pass element. As shown in below figure, the pass element can be an N- or P-channel FET, which delivers the voltage drop as a function of FET’s on-resistance, RDS(on).Basic LDO block diagram |
Pass element can be an N- or P-channel FET in a LDO |
Key LDO Performance Parameters
1) Dropout Voltage – It is defined as the difference between the input and output voltages at the point when an additional or more decrease in input voltage causes output voltage regulation to become fail. In the dropout situation, the pass element works in the linear region and acts like a resistor. For the modern LDO, the pass element is normally implemented with PMOS or NMOS FETs, which can attain a dropout voltage as low as 30mV to 500mV.2) Load Regulation – It is defined as the output voltage variation for a given load variation. This is normally from no load to full load. It can be expressed by below equation;
Load regulation = ΔVout/ΔIout = (Vout@noload – Vout@fullload)/(0 – Iout_fullload)
Load regulation specifies the performance of the pass element and the closed-loop DC gain of the regulator. The higher the closed-loop DC gain, the superior is the load regulation.
3) Line Regulation – It is the output voltage variation for a given input voltage variation. It can be expressed by below equation;
Line regulation = ΔVout/ΔVin = (Vout@vin_max – Vout@vin_min)/(Vin_max – Vin_min)
4) Power Supply Rejection Ratio (PSRR) – It is a sign of the LDO’s capacity to reduce fluctuations in the output voltage produced by the input voltage, as expressed in below equation. While line regulation is only measured at DC, PSRR measured over a wide frequency range.
PSRR = 20log₁₀(Vin/Vout)
Consider a conventional closed-loop system, the small-signal output voltage, ͠Vout can be expressed as;
Vout = {[Gvg/(1 + kv X Gc X Goc)] ͠Vin} + {[(Gc X Goc)/(1 + kv X Gc X Goc)] ͠Vref}
Where;
͠Vin = the small signal input voltage
Gvg = the open-loop transfer function from input to output voltage
Kv = the output voltage sensing gain
Gc = the compensator’s transfer function
Goc = the open-loop transfer function from the control signal to the output voltage
kv X Gc X Goc = is the closed-loop transfer function, T(s)
While seeing above two equations of PSRR, it is clear that the PSRR contains the closed-loop gain, T(s), and the inverse of the open-loop transfer function from input to output voltage, 1/Gvg, as shown in below figure. However the closed-loop transfer function controls at lower frequencies, the open-loop transfer function from input to output voltage controls at higher frequencies.
PSRR vs Frequency |
6) Transient Response – LDOs are generally used in applications where point-of-load regulation is essential, such as supplying power to digital ICs, FPGAs, DSPs and low-power consuming CPUs. The load in such applications has many modes of operation, which need different supply currents. As a result, the LDO has to react fast to keep the supply voltage within the requisite levels. This makes the transient performance of an LDO one of the critical performance parameters. As in all closed-loop systems, the transient response mostly relies on the bandwidth of the closed-loop transfer function. To attain the best transient response, the closed-loop bandwidth has to be very high while confirming enough phase margin to keep stability.
7) Quiescent Current – It is also called as ground current. The quiescent current of an LDO is the arrangement of the bias current and the drive current of the pass element, and is usually kept as low as possible. Moreover, when PMOS or NMOS FETs are used as the pass element, the quiescent current is moderately unaffected by the load current. Since the quiescent current doesn’t pass through to the output, it effects the LDO’s efficiency, which can be calculated by below equation;
Efficiency = (Iout X Vout) / (Iout + Iq) X Vin
The power dissipation inside the LDO is given by: Vin X (Iq+Iout) – Vout X Iout. To enhance the LDO’s efficiency, both quiescent current and the difference between the input and output voltages must be reduced. The difference between the input and output voltages have a direct effect on efficiency and power dissipation, so the lowest dropout voltage is usually chosen.
Applications of LDO
LDOs are mainly suitable to applications that need an output voltage regulated to somewhat below the input voltage. While buck and boost converters have restrictions on the maximum/minimum duty cycle, their output voltage will lose regulation with an input voltage that is near to the output voltage.Even though an LDO cannot supply high efficiency power conversion as compare to a switch mode power supply (SMPS), it is still a essential voltage regulator for many new applications. In noise sensitive applications, it is very hard for an SMPS to attain the essential output ripple to meet a tight noise requirement. Therefore, it is not unusual for an LDO to be adding as an active filter to the output side of a SMPS. For using LDO at output side of the SMPS, please keep in mind that LDO must have high PSRR at the SMPS switching frequency.
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